Cypress Semiconductor /psoc63 /BLE /RCB /INTR_MASKED

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTR_MASKED

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RCB_DONE)RCB_DONE 0 (TX_FIFO_TRIGGER)TX_FIFO_TRIGGER 0 (TX_FIFO_NOT_FULL)TX_FIFO_NOT_FULL 0 (TX_FIFO_EMPTY)TX_FIFO_EMPTY 0 (TX_FIFO_OVERFLOW)TX_FIFO_OVERFLOW 0 (TX_FIFO_UNDERFLOW)TX_FIFO_UNDERFLOW 0 (RX_FIFO_TRIGGER)RX_FIFO_TRIGGER 0 (RX_FIFO_NOT_EMPTY)RX_FIFO_NOT_EMPTY 0 (RX_FIFO_FULL)RX_FIFO_FULL 0 (RX_FIFO_OVERFLOW)RX_FIFO_OVERFLOW 0 (RX_FIFO_UNDERFLOW)RX_FIFO_UNDERFLOW

Description

Master interrupt masked request register

Fields

RCB_DONE

Logical and of corresponding request and mask bits.

TX_FIFO_TRIGGER

Logical and of corresponding request and mask bits.

TX_FIFO_NOT_FULL

Logical and of corresponding request and mask bits.

TX_FIFO_EMPTY

Logical and of corresponding request and mask bits.

TX_FIFO_OVERFLOW

Logical and of corresponding request and mask bits.

TX_FIFO_UNDERFLOW

Logical and of corresponding request and mask bits.

RX_FIFO_TRIGGER

Logical and of corresponding request and mask bits.

RX_FIFO_NOT_EMPTY

Logical and of corresponding request and mask bits.

RX_FIFO_FULL

Logical and of corresponding request and mask bits.

RX_FIFO_OVERFLOW

Logical and of corresponding request and mask bits.

RX_FIFO_UNDERFLOW

Logical and of corresponding request and mask bits.

Links

() ()