Master interrupt masked request register
RCB_DONE | Logical and of corresponding request and mask bits. |
TX_FIFO_TRIGGER | Logical and of corresponding request and mask bits. |
TX_FIFO_NOT_FULL | Logical and of corresponding request and mask bits. |
TX_FIFO_EMPTY | Logical and of corresponding request and mask bits. |
TX_FIFO_OVERFLOW | Logical and of corresponding request and mask bits. |
TX_FIFO_UNDERFLOW | Logical and of corresponding request and mask bits. |
RX_FIFO_TRIGGER | Logical and of corresponding request and mask bits. |
RX_FIFO_NOT_EMPTY | Logical and of corresponding request and mask bits. |
RX_FIFO_FULL | Logical and of corresponding request and mask bits. |
RX_FIFO_OVERFLOW | Logical and of corresponding request and mask bits. |
RX_FIFO_UNDERFLOW | Logical and of corresponding request and mask bits. |